Workers are aware of certain techniques for "scaling" image data. For instance, U.S. Pat. No. 5,305,398 to Klein, et al. (assigned in common herewith; issued Apr. 19, 1994) teaches a scaling processor to change the size of a captured image (digital electronic representation), with associated input means to indicate image size, pixel data, etc. (FIGS. 1A, 2A and 3A are taken from U.S. Pat. No. 5,305,398). Here, FIG. 1A shows an image processor 24 arranged to include a random access storage memory (RAM) 50, a 5.times.5.times.8 bit shift register window assembly 52, a document height detection subprocessor 54, an input/output controller, a normalization subprocessor 58, a background suppression subprocessor 60, a spot/void subprocessor 62, and a scaling subprocessor 64.
Specifically, the document height detection subprocessor 54 is coupled to the input/output controller 56 by signals on bus 66 and is further coupled to the storage RAM 50 and to window shift register window assembly by signals on bus 68. The input/output controller is coupled to the storage RAM 50 and to the shift window assembly 52 by signals on bus 70 while also being coupled to the subprocessors 58, 60, 62, and 64 by signals on bus 72.
The shift register window assembly is additionally coupled to storage RAM 50 by signals on bus 74 and is coupled to each of the subprocessors 58, 60, 62, and 64 by signals on bus 76. Additionally, the subprocessors 58, 60, 62, and 64 are coupled together by signals on bus 78 which represents a functional output associated therewith, while the document height detection subprocessor 54 produces a document height output on bus 80.
Input video data is coupled to the storage RAM 50 and to the input/output controller by signals on bus 82 while the input/output controller further has an input bus 84 which is coupled thereto and which contains externally placed parameter data and command inputs which may emanate from a host computer 28.
Image Processor 24 feeds an Image Storage Module, which is controlled by input from the document processor (e.g., a check sorter) and by associated Host Computer 28.
Generally, the normalization subprocessor 58 is used to correct image data defects associated with such things as a non-uniform photo-cell responsiveness of the camera system 11 or non-uniform document illumination across a segment of a document being scanned during the acquisition of input video data which is placed upon bus 82 by system 11.
The background suppression subprocessor 60 is used to eliminate unwanted scenic or patterned background information from the image of a scanned document, while retaining printed and written information with the image associated with signals on the bus 82. The background suppression subprocessor 60 provides for uniform background, increased image contrast, and increased image uniformity associated with the video data placed upon bus 82. The spot/void filtering subprocessor 62 is used to eliminate small white and dark anomalies which adversely affect the quality and compressibility of the image represented by signals on the bus 82, while the scaling subprocessor 64 allows the image to be scaled relative to the resolution of the image by using one of a plurality of algorithms. The document height detection subprocessor 54 finds the highest and lowest points of transition from the image of the document to the image of the background thusly finding or identifying the overall height of the document whose image is represented by signals on bus 82.
The input/output controller is used to receive externally placed commands and parameter data associated with the processing of the preprocessors 58, 60, 62, and 64 and is further used in the normalization function to allow a remotely located controller (i.e., host computer 28) to sample the input video signals upon the bus 82. The input/output controller, by means of signals on bus 72, selects one of the subprocessors 58, 60, 62, or 64 to be activated in response to external command inputs upon bus 84.
The shift register window assembly 52 is used as a repository for image pixel data and is used in the performance of the various functions associated with subprocessors 58, 60, 62, or 64. In a preferred version shift register window assembly 52 has a dimension of 5.times.5.times.8 bits, since each of the pixels associated with the video image upon the bus 82 is up to eight bits in length, and since the operations associated with the subprocessors 58, 60, 62, and 64 are performed upon a 5.times.5 pixel array.
FIG. 2A is a block diagram of the scaling subprocessor block 24 shown generally in FIG. 1A. Here, the scaling subprocessor block 64, which is used to modify the resolution of the image (i.e., by changing its dimension), contains a scanline counter 772 and a scaling processor 774. The counter 772 is coupled to an end-of-scan signal on bus 108 and generates a single count for every "end-of-scan" pulse that appears on bus 108, thereby producing (on bus 776) a running identification of the columns associated with the acquired image. Bus 776 is coupled to an input of scaling processor 774. Additionally, the scaling processor 774 is coupled to row count signals on bus 104 and to bus 76. Processor 774 uses the row counts, on bus 104, and column counts, on bus 776 to correctly place the position of each of the pixels within the acquired image. The scaling processor 774 (which may be located off the image processing chip) uses the column count and row count associated with signals on busses 776 and 104, respectively, to produce a scaled output.
Referring now to FIG. 3A, there is shown a flowchart 800 which details the operation of the scaling processor 774 which, in this embodiment, is microprocessor based. The initial step 802, of flowchart 800, is followed by step 804 which requires the scaling processor 774 to acquire the row and column counts of buses 776 and 104 respectively. Step 806 follows step 804 and requires the scaling processor 774 to select pixels of data from the RAM and shift window register assembly 50, 52, by bus 76, wherein these pixels are selected based upon the row in column counts on the buses 776 and 104 respectively.
Step 808 follows step 806 in which the scaling processor 774 processes the acquired pixels in a scaling usual manner and then outputs the processed data onto bus 809 (FIG. 2A) to an output multiplexer 148. In the preferred embodiment of this invention, the scaled output value associated with step 808 is a typical median scaled value of the selected pixels. This is proven to retain edge features better than standard averaging techniques. Step 808 is followed by step 804. This is, three columns (i.e., 440, 442, and 444) of pixels and three rows (i.e., 450, 452, and 454) are processed by processor 774 at any instant of time. Processor 774 then discards the center pixel 458 and defines four quadrants as being defined by pixels "P.sub.42 ", "P.sub.32 ", and "P.sub.43 "; "P.sub.22 ", "P.sub.32 ", and "P.sub.23 "; "P.sub.23 ", "P.sub.24 ", and "P.sub.34 "; and "P.sub.43 ", "P.sub.44 ", and "P.sub.34 " respectively. Each quadrant is then assigned a single gray-scale value defined as the median of the gray-scale value of the pixels within each quadrant. Processor 774 then outputs one gray-scale value per quadrant at a time. This median scaling technique has proven to yield substantially sharper images than many prior scaling techniques.
The foregoing may be understood as a "scaling-down" processor for receiving a first plurality of pixels associated with image data, each of these pixels having a gray-scale value associated therewith. This scaling processor comprises:
(a) input means for receiving the first plurality of pixels and for arranging these pixels into a first matrix; and
(b) processor means, coupled to this input means, for creating a second matrix by deleting a center pixel of said first matrix and thereafter for creating a second plurality of pixels to be contained within this second matrix.
U.S. Pat. No. 5,305,398 may also be understood as teaching an image processing device for use with an array of pixel data arranged in rows and columns and corresponding to an image, this device comprising:
first input means for receiving scanned lines of pixel data;
second input means for receiving a signal indicating an "end of a scan line" from an image sensor that generated the pixel data;
memory means for storing the pixel data in a first matrix;
address generator means for generating an address for each pixel in a scan line;
counter means for identifying each of said end of scan line signals;
output means for providing information regarding each of said scanned lines of pixel data, each of said generated addresses, and said first matrix of pixel data; and
scaling processor means coupled to the output means and operative to create a plurality of sub-matrices from the first matrix of pixel data, each said submatrix being centered about a center pixel, and to generate a second matrix of pixel data smaller than the first matrix by combining pixels in each of the plurality of sub-matrices in a predetermined manner to scale-down the image, this combination of pixels excluding the center pixel of each sub-matrix.